Semiconductor device manufacturers are constantly striving to increase product performance while decreasing their cost of manufacture. A cost intensive area in the manufacture of semiconductor devices is the packaging of semiconductor chips. Integrated circuits are fabricated on wafers which are then singulated to produce semiconductor chips. Subsequently, the semiconductor chips may be mounted on electrically conductive carriers, such as leadframes. Packaging methods providing high yield at low expense are desirable.
Diffusion soldering is one technique for mounting a semiconductor chip to a carrier, and involves depositing a structured diffusion solder layer on metal surfaces of the chips to be connected to a carrier, such as a chip BSM (back side metallization), for example. Two primary techniques are available for the structured deposition of the diffusion solder layer, ECD (electro chemical deposition) and PVD (physical vapor deposition). Each technique is costly and has drawbacks.
With ECD, deposition of the diffusion solder layer across the entire chip surface is necessary, as required materials cannot be successively deposited and patterned in a desired order since the plating bath dissolves the previous layer. However, subsequent etching of the full-face diffusion solder layer can lead to under-etching of the BSM and cannot be used with all materials. With PVD, the high temperatures required can be damaging and residues can be left behind after lift-off of a patterning mask. Additionally, regardless of the technique, when applied as part of front end processing, the diffusion solder layer can be damaged during wafer singulation, particularly as wafer thicknesses continue to decrease.
For these and other reasons, there is a need for the teachings of the present disclosure.